Design Verification Engineer

Design Verification Engineer responsible for evaluating and enhancing AI model training for digital chip design and verification, with experience in digital RTL design or design verification and proficiency in Verilog/SystemVerilog and UVM.

Requirements

• 3–10 years of experience in digital RTL design or design verification
• Strong proficiency in Verilog/SystemVerilog and UVM
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
• Experience with ASIC design flows and EDA tools
• Familiarity with leveraging LLM-based tools for chip design and verification workflows