Company:QT Technologies Ireland LimitedJob Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:About the roleQualcomm’s Mixed-Signal IP (MSIP) Design Verification team is seeking M...
24 days ago
Mixed-Signal Design Verification Engineer
Full time · IRELAND
Job description
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Estimated salary
Based on 14 similar vacancies
4 619 – 8 726 $/month
4 619 $25%
6 062 $median
8 726 $75%
The range shows the lower and upper market bands: 25% of vacancies pay below the first value, the median is the typical salary, and 75% marks the upper band.